The various architectures of the implemented CORDIC algorithm use
resources in the target FPGA device differently. We chose the
bit-parallel iterative CORDIC architecture to implement a complete
oscillator using an FPGA since this structure shows a trade off
between area usage and maximum achievable speed. Table
1.4 illustrates the exact results obtained using
a XILINX XC4010E as the target device. The values are taken from
report files generated by the FPGA implementation software and provide
detailed information about area usage and timing issues.
Table 1.4: Performance and CLB usage for the bit-parallel designs.