Center for New Music and Audio Technologies

next up previous
Next: Error Up: Results Previous: Results

Area Usage and Performance

The various architectures of the implemented CORDIC algorithm use resources in the target FPGA device differently. We chose the bit-parallel iterative CORDIC architecture to implement a complete oscillator using an FPGA since this structure shows a trade off between area usage and maximum achievable speed. Table 1.4 illustrates the exact results obtained using a XILINX XC4010E as the target device. The values are taken from report files generated by the FPGA implementation software and provide detailed information about area usage and timing issues.

Table 1.4: Performance and CLB usage for the bit-parallel designs.
  CLB LUT FF Speed Latency max. Throughput
  $ [1]$ $ [1]$ $ [1]$ [MHz] [$ \mu$s] $ [$Mio. Samples $ \cdot s^{-1}]$
Control structure 26 49 17 61.2 0.03 30.6
Cordic 138 252 52 36 0.44 2.25
Oscillator 153 267 69 28 0.64 1.55



next up previous
Next: Error Up: Results Previous: Results
Home
Norbert Lindlbauer
2000-01-19