Center for New Music and Audio Technologies

Implementation

When implemented in an FPGA the synchronizer circuit can be basically represented by two components: start_detect and counter, as shown in Figure 1.2. Component start_detect listens to the input and every time a logic low is asserted the component counter will be enabled which controls the examination of the data values, and hence the whole design. The counter enables register1 and register2 for storing the MIDI bits, enables the component validity_check for performing a validity check and finally sets the component start_detect to its initial state after each received MIDI byte.

Figure 1.2: MIDI synchronization design

The master clock for the design is the 12 MHz frequency generated by the prototyping board's crystal whereas the MIDI clock is specified as 31.25 kHz. This gives a ratio of 384 of master clock to MIDI clock and as the value of the input is looked up in the middle of each bit, the counter waits 192 master clock cycles before the enable signal for the register1 component goes high and the current input value is stored in register1. This procedure is repeated for every bit of a MIDI byte and obviously a simple counter is needed to keep track of the current position within a MIDI byte. After the last bit has been received a validity check needs to be performed in order to ensure the message has been transmitted correctly. The validity check can only be based on the recognition of the start and stop bit, for the simple reason that there is no other repeating sequence in a MIDI protocol's frame. The start bit does not need to be checked, since the component start_detect is already sensitive to it. Thus, only the stop bit has to contain the right value. If the byte is recognized as sent correctly, it will be stored in the second register, without start and stop bits^1.1, while a new MIDI byte can be received. The signal data_valid is set to high for one clock cycle whenever a MIDI byte is received correctly and can be accessed from register2 at the MIDI_sync port. This prevents the adjacent component from reading the same MIDI byte twice. Finally the component start_detect has to be initialized before the next start bit is asserted at the input. Since the stop bit could be wrong a sensitivity to a high-low transition is necessary. Thus, the component start_detect will check if there is a high before low and only if this is the case will the counter be started again and the next MIDI byte is synchronized.
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