Center for New Music and Audio Technologies

Performance Issues

Compared to modern networking capacities, MIDI is a slow protocol. At the same time, the human sense for musical real time operations is sensitive to latencies above just a few milliseconds. MIDI's transmission speed is 31.25kHz, so the latency for one single MIDI byte equals 320$\mu$s. Considering, that most MIDI messages consist of several bytes, it can be concluded why the latency in MIDI systems is a critical issue. From all this it follows that the latency for the MIDI Synchronizer is to be kept as low as possible. Obviously, since the MIDI protocol obeys the laws of serial data transmission the minimum time between recognizing the start bit and setting the data_valid signal to logic high can be considered as:

time for detecting 10 MIDI bits	:	$9.5\cdot 384$ clock cycles
performing the validity check	:	1 clock cycle
loading data into register2	:	1 clock cycle
Total	:	$3650$ clock cycles.

With a clock rate of 12MHz the latency equals 304.167$\mu$s which is slightly less than the time needed for the transmission of an entire MIDI byte. The residual can be used to reset the counter, clear the component one_detect and be ready for the next incoming data. Of course, the FPGA-specific delay times like setup, hold and propagation delay times add latency as well, but since those times are below 10ns one can simply neglect them.

The designs MIDI Synchronizer and MIDI P2S had been implemented together and separately in a XILINX Spartan FPGA and tested using the MIDI Hardware described in section 1.4. Table 1.1 shows the performance achieved and the resources needed. The values are taken from report files generated by the XILINX Foundation Series software when implementing the designs.

Table 1.1: Performance of the various designs for synchronizing MIDI in an XILINX Spartan

Design	CLBs	CLB-FFs	4-Input LUT	Speed [MHz]
MIDI Synchronizer	20	34	27	50.36
MIDI P2S	15	22	29	41.46
MIDI Interface	40	56	56	36.05

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